As a result of the rapid development of the semi-conductor technology, the current computer has assumed a rather important role because it improves our work efficiency considerably. In real use, a huge quantity of data has to be processed and operated (such as image processing). In order to elevate the performance speed, a plurality of identical processors for parallel operation have been used in the current computer system.
Usually, when a CPU controls a plurality of processors in parallel, the CPU has to continuously check whether all processors have completed their operation before issuing a next instruction to them. The system otherwise might suffer from a downtime because of some processors having slower operation and not being set in ready condition. Conventionally, the design of a plurality of processors connected in parallel (as shown in FIG. 1) uses a clock 10 as a time sequence control means for all processors (for example, three processors); the CPU 20 has to check the flags of all processors continuously so as to keep the conditions updated for effective control thereof. Since the CPU has to check all processors one by one, the CPU would suffer from a heavy work load. In other words, the CPU of the prior art wastes a lot time servicing the whole system while still working at lower operating levels.
Therefore, the drawbacks of the aforesaid conventional parallel processors inspired the inventor's interest in developing the present invention, which can minimize the check work to all processors by CPU so as to elevate the performance of system in operation.